Benefits

•Rapid hierarchical planning, prototyping and optimization of 2.5/3D heterogeneous assemblies

•System connectivity management and visualization with cross-domain pin/signal mapping/shorting and system-level logical verification

•User-definable rules for custom optimization of pin and ball-out assignments

•System-level predictive SI/PI

•Predictive data path flow planning

•System Verilog integration

•50M+ pin design support

•Extensive input and output data formats

•System-level LVS/STA verification through Calibre® 3DSTACK

•Direct integration with Xpedition Package Designer for detailed implementation

Introduction

Xpedition® Substrate Integrator (xSI) provides a graphical, rapid virtual prototyping environment tuned for the exploration and integration of multiple heterogeneous ICs/chiplets and interposers into High Density Advanced Packages (HDAP). It utilizes a System Technology Co-Optimization (STCO) methodology to co-design complex 2.5/3D package assemblies while targeting different system PCBs. Designers and micro-architects can quickly and easily assemble complete cross-domain substrate systems and drive ball map plans and pin optimization through a rule-based methodology.

Using an STCO methodology ensures ICs, packages, and PCBs are optimized in the context of each other. This results in fewer layers and tighter control of the design process resulting in optimized device performance, lower-cost package assemblies and PCBs with the benefit of system level performance.

Targeting Multiple System Platforms With One Semiconductor Package

A company designing semiconductors for smart, wireless, mobile products might want to target the same package configuration for use in several devices, such as a tablet, a laptop, a smart phone, etc. (Figure 1). The physical constraints for each application are significantly different and the electrical constraints can also be different.

Figure 1: Complex heterogeneous 2.5/3D assemblies can be defined, managed and optimized for one or multiple target system PCB’s

Using xSI, this process is efficient and takes just a fraction of the time it would take to do manually, if it could be done at all.

Package configurations can be rapidly evaluated using the particular target PCB, allowing the same die/chiplets to be used in the most efficient way given the end- product requirements. Optional tools enable package configurations and PCB designs to be analyzed for power and signal integrity, electromagnetic characteristics (with 3D modeling), thermal characteristics and performance, plus manufacturability. Design versions can also be compared and verified.

Multi-Mode System-Level Connectivity Management

The unique approach of xSI for cross-domain connectivity management allows design teams to capture and manage connectivity in the environment they are most comfortable with. For example, package designers can use a table-based solution while board designers use a graphical schematic to work together on the same project. For early planning and prototyping, system-level connectivity can be managed internally and remain trans- parent to the end user. See Figure 2.

Figure 2: Users manage system-level connectivity in the environment in which they are most comfortable.

The solution also manages signal combining (shorting) in the case of name changes from domain to domain as well as power/ground shorting. A convenient and familiar drag-and-drop technique can also be used for ball-map planning. The multi-design project manager manages the hierarchy and relationships between domains while maintaining database integrity of the individual designs. This facilitates fast and easy data exchange with the implementation tools.

Prototyping and Planning

Determining the best package based on cost and performance often requires the development of a custom package definition. In some cases, this can be a simple case of ball/pin depopulation. As an example, a CPU or GPU may require a completely asymmetrical array of pins to satisfy its market needs.

Shown in Figure 3, xSI contains powerful capabilities to dynamically add, delete, copy, move, and adjust pin pitch.

Figure 3: Pin pitch can be dynamically adjusted

Heterogeneous Integration and Co-Optimization

Virtual Die Models (VDM) enable early asynchronous planning and optimization of ASICs or chiplets by disaggregating them hierarchically chip floorplan blocks or “chunks” These chunks can be updated as the silicon design progresses using incremental VDM (block) updating (Figure 4). Package planning can now start earlier, even before the entire chip is designed or even started reducing overall design cycles and preventing potential respins

Figure 4: ASIC’s or chiplets can be disaggregated into “chunks” that can be asynchronously planned and co-optimized between package and ASIC/chiplet design teams reducing overall design cycles

Rather than managing pin assignments in multiple tabs in a spreadsheet, xSI displays the complete system in a single view with flight lines indicating connectivity between devices, as seen in Figure 5.

Figure 5: Visualization of the entire package-to-PCB system can be seen visually or in a table, making routing easy to understand

Cross-Domain Interconnect Visualization

From this floor plan view, rules-based optimization can be run from any direction by signal, bus, or interface. Escape and breakout routing can be included easily in the optimization process.

Rules Driven Pin Planning

An easy-to-use pin planning and optimization rules engine lets engineers define which pins on the package can have which signals or interfaces assigned to them. Rules can also be written to ensure that critical nets are assigned adjacent to ground nets or that corner pins will only accept the ground signal.

Figure 6 shows how rules are reflected in colors that designate which rule applies to a particular ball. Several types of rules are illustrated. For example, if data busses were not allowed on inner pins, any attempt to do so would result in an error reflected by pins turning red with the reason displayed.

Figure 6: Xpedition Substrate Integrator allows users to easily construct rules based on a variety of parameters

Predictive Data-Path Planning

Ability to group/bundle signals into “data paths” for graphical route/wire flow planning (Figure 7). This provides the designer with greater predictability of potential route congestion as well as a more predictive SI/PI analysis.

Figure 7: Data path bundle/bus planning enables more accurate predictive analysis

Predictive Early System-Level Analysis

A key benefit of prototyping and planning is having access to predictive analysis very early in the design cycle. xSI allows very early timing, signal/power integrity to be evaluated at the package and even the system PCB level through direct integration with the HyperLynx SI/PI and DRC technologies. Designers can quickly evaluate integration schemes and there positive or negative impact on performance before physical design starts

2.5D/3DIC Stack Verification

Vertical integration, especially with heterogeneous stacked devices & substrates, requires comprehensive assembly-level LVS verification of the system-level packaging interfaces (Figure 8). Interface geometries between chip designs, including bumps, balls, through-silicon or through-interposer vias (TSVs/TIVs), and copper-to-copper bonding, must be taken into account.

Figure 8: 3D LVS verifies that the signal interfaces between the different levels of substrate hierarchy connect as expected and that any manufacturing or assembly mismatches or signal to pin assignment mistakes are captured.

In conjunction with Calibre 3DSTACK, xSI uniquely identifies geometries per layer per die placement in the assembly, allowing accurate checking between dies (Figure 9). With the ability to differentiate the layers of interest per individual die placement, Calibre 3DSTACK enables designers to verify the physical attributes (offset, scaling, rotation etc.) of each die, while also tracing the connectivity of the interposer or die-to-die interfaces.

Figure 9: Using Calibre 3DSTACK with xSI allows for 3D LVS between multiple die and substrates