Benefits

• Reduced overall repair costs across process and product verification

• Reduced overall cost of test 

• Reduced time to market through making testability considerations part of the design flow and not a costly re-spin late in a subsequent revision 

• Reduced scrap and recycle costs with improved diagnostics of failing boards

• Reduced production impact of having to build replacement boards for those that have been scrapped

Features

• Schematic only testability analysis

• Test point requirements calculations for each net

• Support for IEEE 1149.1 boundary scan components

• Flexible test methodologies including TPC and PCOLA-SOQ

• Quality index, defect index and testability coverage analysis

• Parallel component analysis 

• Kelvin (4 wire) test point requirements

• Power and ground test point requirements

Overview

Companies creating electronic products want to design and manufacture those products with as much inherent quality as the price point allows. If the electronic manufacturing process was perfect, the need for manufacturing test would be minimized but unfortunately it is not. Therefore even if we have low defect rates incomplete test coverage  does not have the ability to discover which boards are not defective free. Why is that? It is due to testability issues being considered late in the design flow, or even ignored completely. Products that escape our manufacturing process with undiscovered faults affect quality.

Test strategy and test point assignment are typically considered late in PCB design environments. Sometimes, the first or second revision of a product will be completed before testability issues are considered, which means that optimizing a test strategy is negatively impacted by design constraints. For PCB design, this had been a similar challenge with design for manufacture (DFM). Post-processing Gerber files created hundreds or thousands of issues that were difficult to resolve because of knock-on effects to the design. This issue was resolved by left-shifting the DFM analysis to be concurrent with the layout design, resulting in a smaller list of issues being resolved more easily as the PCB layout process evolves. Now this same approach can be used for design for test issues in the PCB design flow with Valor™ DFT, exclusively for the Xpedition™ Enterprise design flow.

Proactive DFT for PCBs

Testability considerations rarely occur at the schematic capture phase. When they do, they require test engineers to perform manual analysis of dozens of schematic pages, which cannot keep up with the progress of the layout. Once the input is received, acting on change requests is constrained. This has resulted in a reactive, rather than proactive, testability design environment.

Testability considerations need to be available during schematic capture and then drive test point requirements in to layout. DFT must become proactive, not reactive. Once in layout, on-going test point management can continue to monitor the testability considerations as the PCB layout is realized. If test points are not needed between two components, they can be positioned closer

together. If they do need test points between them, they can be pushed further apart. Doing this at the initial layout floor planning stage will allow the test requirements to have a higher likelihood of success.

The number of test points on each net is compared to the required number of test points.

Again a traffic light highlighting scheme is used to indicate correct, extra or insufficient.

Process verification versus product verification 

With Valor DFT and Xpedition, boundary scan test, flying probe test, and in-circuit test all can be used to design testability in to the design of a PCB. Along with inspection techniques, they form the basis of PCB manufacturing process verification. They answer the question of whether the board was built correctly quickly and with excellent diagnostics. These techniques isolate individual components and pins to determine if a process defect has occurred.

Functional test, otherwise known as product verification, primarily is used to determine if the product works as its design intended. Functional test is used across many components, maybe even the whole board, to run at speed tests to prove the board meets its design performance targets. As a result, diagnostics are much poorer. When a process fault is caught by functional test, it may take a skilled repair engineer much more time to find that defect than if it was detected by one of our process verification methods. If functional test is covering for gaps in your process verification strategy, significant savings can be achieved with Valor DFT.

Benefits of boundary scan

Although more than 30 years old, boundary scan is still used extensively on many PCBs. Using this method can help reduce the test point requirements of a board without losing test coverage.

For example, if the connections on a net all have boundary scan capability, then a test point on that net does not need to be added. The designer can use the real estate of a test point on one net and apply it to another area of the board where a test point must be placed. A challenge for a designer is being able to drive boundary scan software as part of their design flow. 

Valor DFT can read the boundary scan description language files (BSDL) to determine the test point requirements on a net itself. It does not need to run the detailed boundary scan analysis at that time. Feedback is quicker without the need to create models for all the non-boundary scan components. By including it with Xpedition, Valor DFT can be run as part of the design flow.

Valor DFT also analyzes the test access port TAP of each boundary scan component. No checks are performed in the design flow for boundary scan today.

Valor DFT is the only tool that provides this analysis as part of the Xpedition Enterprise PCB flow.

Final test coverage for each component and pin is shown with traffic light highlighting.

Before and after test coverage 

Achieving 100% access does not mean you have 100% test coverage. A repeatable metric to calculate test coverage provides the ability to improve over multiple designs. User-defined defects per million opportunities (DPMO) provides Valor DFT with a heat map of the components and defects that cause the biggest impact in manufacturing. This allows aligning the test strategy with the defect opportunities and the ability to create a test strategy that provides optimal results at a cost aligned with the product goals.

Summary

Valor DFT is the missing piece in your PCB design flow. There are many integrated solutions to prove that your design functions as designed. However no ECAD tool has integrated design for test analysis except Xpedition Enterprise from Siemens Digital Industries Software.

System requirements

• Windows 7, 32 and 64 bit

• Windows 10 64 bit

• 4 GB RAM, dual-core processor