Benefits

•Supports physical design of High-Density Advanced Packages (HDAP) including FOWLP, 2.5D/3D, silicon and organic interposers, embedded substrate bridges, System-In-Package and modules

•Advanced dynamic metal fill with DFM-ready results including multi-pass degassing, metal balancing and offset hatched planes

•Real-time design visualization and editing in 2D and 3D

•Concurrent multi-user team design and patented “sketch routing” shrinks design cycle

•In-design geometry-based DRC Removes/reduces signoff-driven ECOs

•Physical IP block reuse leverages proven IP and reduces design time

•Direct creation of SI/PI simulation models with integrated 3D EM solver

•Fast high-quality mask generation using either GDSII or OASIS

•Full mask LVS and package assembly signoff through direct integration with Calibre 3DSTACK

Key features

•Proven capacity and interactive performance on the largest designs

•Multi-user concurrent team design

•ODB++ import for legacy design migration

•Fast accurate GDSII and OASIS output

•Rapid, on-the-fly connectivity creation via Layout Driven Design

•2D/3D editing and visualization all within core layout

•Patented sketch-routing technology for the industry’s highest routing productivity

•Fast, accurate and mask-ready area fill/plane processing including degassing, metal balancing and offset hatched planes

•Embedded 3D quasi-static field solver for package model creation

•User-customizable geometry DRC engine for in-process verification of complex rules

•Direct integration with Calibre for mask signoff, assembly LVS and debug

Introduction

Xpedition® Package Designer (xPD) is a complete, powerful, and proven physical implementation and verification solution.

It supports full heterogeneous integrations of die/chiplets and supports all die attachment technologies.

It provides comprehensive support for modules/system-in-package (SiP), package-on-package (PoP) as well as RDL based fan-out wafer level packaging (FOWLP) and 2.5D/3D with silicon or organic interposers. All of this capability is available without requiring costly product add-ons or upgrades.

Layout Driven Design (LDD) capability enables designers to start from nothing adding connectivity on the fly, or import it from a spreadsheet, schematic even from System Verilog.

Optional technologies that integrate with xPD

HyperLynx® power integrity, signal integrity, and 3D full-wave EM analysis tools, Simcentre Flotherm® CFD thermal modeling, Valor® NPI organic substrate fabrication checking, and Calibre® nmDRC/RVE for foundry/OSAT approved mask signoff and assembly LVS verification.

Meeting the HDAP Challenge

xPD has been architected to specifically address the disruptive challenges of emerging packaging technologies. It delivers innovative design automation, verification, optimization, and yield enhancing technology to ensure your design meets all performance, manufacturing, and reliability requirements.

Fast and Flexible Design Creation

Powerful import utilities enable the rapid capture of die, interposer, or BGA from a variety of data sources including csv/txt, AIF, ODB++, DXF, GDSII and System Verilog. Easily create devices on-the-fly with parametric construction including advanced features for asymmetrical pattern support.

Prototyping and planning with Xpedition Substrate Integrator (xSI)

Prototyped, planned and optimized IC package designs can be imported from Xpedition Substrate Integrator (Figure 1), significantly accelerating initial design while ensuring co-design optimization with all die/chiplets and system PCB.

Figure 1: Package planning and prototyping in Xpedition Substrate Integrator

2D/3D Interoperability

Simultaneous 2D/3D editing and checking can be done without add-ons or separate windows.

Concurrent team design

xPD includes patented multi-user concurrent team design that can significantly reduce overall design time by leveraging designer skill and geographic locations.

Performance and Capacity for the Largest Designs

Many of today’s packages for high-performance computing (HPC), networking, or artificial intelligence (AI) applications can exceed 1,000,000+ pins which can be challenging for legacy design tools slowing them down. xPD delivers the capacity, performance, and efficiency and is proven on designs exceeding 2,000,000 total pins.

Comprehensive Wire Bonding

SiP/module packaging is popular for mobile, automotive or IoT applications often utilizing die-to-die wire bonding as a method for minimizing substrate layers and cost. xPD includes a comprehensive suite of creation, automation and editing capabilities for fast, accurate generation of the most complex bonding scenarios (Figure 2).

Figure 2: The real-time 3D environment in xPD provides instant feedback on wire bonding design challenges.

High-Performance Routing

Patented sketch-routing technology combines the power of automatic rout- ing with user control and guidance for high-quality results with exceptional productivity. It’s ideal for non-uniform, flow-oriented routing common to both single and multi-die packages. The sketch-plan feature makes it easy to do floor planning and coordinate large busses by defining editable paths for establishing intent and an overall route flow. It allows the designer to easily optimize and order traces into high-density, multi-row bump or ball patterns.

Powerful plowing algorithms push and shove traces and vias with automatic plane- clearing and healing to deliver high quality results. Sketch routing also provides smooth movement of large trace groups with automatic removal of extra segments, even across rule 

areas. It provides automatic differential pair routing with symmetrical pad entry and short convergence, including broadside or adjacent pair routing (Figure 3).

Figure 3: Sketch plans and differential pair routing and editing are accomplished with speed and ease.

Impedances can be controlled by layer and pair-spacing rules can be established by both layer and net class. If one trace is edited, the other trace in the pair automatically moves with it. Adjacent-layer differential pair routing capabilities add another valuable option for routing critical signals on dense substrates.

High-Speed Design

Many designs have strict requirements for maintaining signal quality and performance. High-speed design is an integral component of xPD with support for electrical performance constraints and dynamic DRC of high- speed rules. It provides both automatic and interactive tuning of high performance interfaces. Tuned nets are maintained automatically throughout the design process.

Rules by Area

The rules-by-area capability greatly improves routing around flip-chip bump patterns and other arrayed devices. Rule areas represent complete rule sets that are obeyed by online batch DRC and during interactive and automatic routing. Rule areas can be defined by layer and assigned to any polygon, rectangle, or circle. Trace widths, clearances and vias automatically change when within the rule area.

Figure 4: Rule areas are obeyed by online and batch DRC and greatly improve routing around arrayed devices such as flip-chip bump patterns.

Efficient Via Definition and Management

Routing advanced-packaging substrates typically requires the use of complex via patterns in a variety of configurations such as stacked, staggered, spiral, or staircase. Many substrates have core layers that require a larger via than the build-up layers, adding additional complexity to these patterns. The constraint-driven approach of xPD to these complex patterns eliminates the error-prone, time-consuming process of having to build dozens (or even hundreds) of unique pad stack definitions corresponding to all potential layer combinations.

xPD utilizes a set of comprehensive via rules to generate patterns as needed using basic pad stacks definitions (Figure 5). This results in a much more efficient approach without the pad stack library overhead. An additional benefit is the ability to automatically remove unused vias from the pattern once routing is satisfied, freeing up space on adjacent layers.

Figure 5: Constraint-driven complex via generation

Dynamic Metal Area Fill

Advanced packages have a number of unique area-fill requirements that are beyond the capability of legacy tools’ generalized fill algorithms. xPD delivers industry-leading accuracy and performance in area- fill implementation and processing.

Native capabilities eliminate the need for error-prone secondary “smooth” processing of complex patterns. Dynamic planes enable rapid push-and-shove of traces and vias with automatic plowing and healing of the metal areas while maintaining design rules.

Many of today’s FOWLP technologies require unique stress relief and degas- sing features in their designs. xPD supports a number of these features, including octagon cut- outs and graduated degassing voids (Figure 6)

Figure 6: Multipass graduated degassing voids insertion

Predictable Quality and Accuracy of Results

xPD uses true arc and circle database constructs that minimize GDS/OASIS tapeout errors due to polygon faceting. Its patented bump-compensation technology expedites die changes while ensuring accurate trace and via alignment. Optimized GDSII and OASIS output algorithm’s ensure accurate output and representation of non-Manhattan geometries.

OSAT’s and foundries are now providing vendor/technology specific Assembly and Process Design Kits (ADK/PDK). Elements and constraints from xPD, HyperLynx DRC, and Calibre can be captured and incorporated into these ADK/PDKs and enables the foundries and OSATs to develop and deliver process optimized rules to their customers.

Manufacturing Readiness with Shift-Left DRC

Manufacturing design rules continue to evolve as OSATs/foundries refine or introduce new processes. Many of these rules present unique challenges to legacy design tools. To address the rapidly changing and complex design rules, xPD includes HyperLynx DRC technology which combines a powerful geometry processing engine with a field solver allowing for custom DRC rule development where rules can also be encrypted to protect IP.

This allows package designers to pro- duce a manufacturing ready design without the ECO iterations of a GDS-only verification flow.

Fast, Full-Package Electrical Model Generation

xPD includes the proven HyperLynx Fast 3D Solver for full or partial-package model extraction (Figure 7). It’s ideally suited for power integrity, low-frequency SSN/SSO, and complete-system SPICE model creation while accounting for skin effect impact on resistance and inductance. Multi- core parallel processing drives extremely fast run times, allowing multiple “what if” scenarios to be run in a minimal amount of time. This enables package designers to quickly deliver models for inclusion in signal integrity simulation by the package’s consumer, often a system designer integrating the package into a PCB design.

Figure 7: xPD includes a built-in, HyperLynx, quasi-static, 3D full-package simulation model generator that allows designers to quickly and simply generate a model for inclusion in signal integrity simulations.

Final Mask Signoff

Many OSAT and foundry HDAP technologies utilize IC-like fabrication constraints on metal areas to control yield, process out-gassing, and improve design quality and typically require mask files in GDSII or OASIS formats. As with IC fabrication, the GDSII/OASIS mask data undergo rigorous verification against very detailed process design rules (ADK/PDK).

Final mask and 3D package assembly verification (LVS) is performed with Calibre (Figure 8) which is the signoff standard for most foundries and OSATs. With real-time integration with xPD delivers fast, efficient, and accurate back- annotation and error display.

Figure 8: Full verification signoff is streamlined through direct integration of Calibre DRC signoff validation with the designer’s xPD desktop.

3D Electromagnetic Simulation Optional HyperLynx 3D electromagnetic simulation solutions for signal integrity, power integrity, and EMI (electromagnetic interference) address the challenges for chip-package-board design, enabling users to generate S-parameter models quickly and accurately for full system analysis.

Thermal Analysis

As products get faster and smaller, thermal management issues increase due to greater chip-package interactions (CPI).

Adding FloTHERM to the xPD flow provides thermal- analysis capabilities for the complete IC package, from detailed, substrate-level, power hotspots to complete thermal modeling of packages for use at the PCB and system level (Figure 9).

Figure 9: Complete package signoff can include detailed thermal analysis and modeling using FloTHERM.